1. Field of the Invention
This invention relates to tools for designing digital circuits and analyzing digital circuit designs, and particularly to transposing wires in digital circuit designs.
2. Description of the Related Art
One of the goals in designing synchronous integrated circuits, and particularly very large scale integrated (VLSI) circuits, including application specific integrated circuits (ASICs), general purpose processors, embedded processors, and digital signal processors (DSPs), is high speed operation. To that end, a variety of computer aided design (CAD) tools are used to design, analyze, and simulate integrated circuits. In the process of designing integrated circuits, often referred to as electronic design automation (EDA), a particular integrated circuit (or section thereof) is typically described by a netlist. The netlist is a list of circuit components or cells and interconnections between the circuit components. The various cell input terminals and output terminals through which cells are connected to each other are often referred to as pins or nodes. The speed at which a given circuit can operate depends in large part on the timing of signals arriving at, and being transmitted from various cells in the circuit.
For example, a bus, i.e., a group of two or more wires (sometimes referred to as nets or bits) that carry closely-associated signals in an electronic design, included in an integrated circuit design can require specific timing characteristics to maintain maximum operating speed for the circuit. If the circuit design depends on well defined relationships among the signals transmitted on the bus lines, anything that affects the signal timing on individual lines of the bus, and/or the relationship among signals on the bus, can affect the overall performance of the circuit. In the case of bus lines, one cause of relative signal timing delays is impedance differences among bus lines. If the impedances of the wires in a bus differ significantly, then signal arrival times, signal edge rates, and clock skew can be very different from one bit line to the next. Apart from the electrical characteristics of the material making up a wire, the impedance of the wire depends on its length, and inductive effects (both self and mutual) associated with the wire. These effects can be particularly significant in buses where the outer wires of the bus present a different impedance than the inner wires of the bus.
Since EDA routing tools are often used to route clock, signal, data, and power paths between various elements of an integrated circuit, one way to alleviate the impedance mismatch among bus wires is via the design rules used in conjunction with the tools. Examples of such routing tools include FlexRoute by Synopsys, Inc., and Envisia Silicon Ensemble (including the Integrated Circuit (IC) Craftsman package) by Cadence Design Systems, Inc. For example, maximum wire length can be restricted to control the total resistance in a line; wire width and length matching can be used to match pairs; and wire spacing can be adjusted to control capacitance and crosstalk between lines. These techniques often have limited effect on the problem, and can cause the area on the die needed for the integrated circuit to increase.
Another common solution is to design a unique driver for each wire in the bus. If all of the lines on the bus are not identical in terms of electrical loading, then the driver for each line has to be individually adjusted to match the characteristics of the specific bus line. Of course, having unique drivers for each wire in the bus can significantly complicate the circuit design process. Moreover, there can be circuit area costs and power consumption costs associated with the unique drivers.
Still another solution is to transpose wires in the bus, thereby giving the wires similar impedances, and obviating the need for individually designed drivers for each of the bus lines. Unfortunately, prior art methods for transposing bus lines have relied on the manual efforts of a circuit designer to select buses from a circuit design, and decide where and how to reroute the bus lines. This process can also be very time consuming, does not guarantee optimal re-routing of bus lines, and thus, may eliminate any benefit gained from not having to design specific drivers for each of the bus lines.
Accordingly, it is desirable to have integrated circuit design tools and techniques for automatically transposing wires in order to reduce cross coupling and to balance bus loading.
It has been discovered that an automatic and parameterized computer implemented method for transposing wires in an integrated circuit design can yield bus lines with similar impedances, and therefore similar signal transmission characteristics. Using a specially designed CAD tool, a user can specify a transposing pattern, intervals at which to transpose wires, and a metal layer through which to accomplish the transposing in the integrated circuit. Using a routing database the tool then automatically determines the locations in the design where transposing needs to be performed, re-routes the wires being transposed while optimizing the circuit design space being used, and re-routes (or causes the re-route of) any other wires affected by the transposing process. The result is a new version of the routing database reflecting transposition, but with no change to the circuit""s netlist.
Transposition of bus lines may also be desirable to make lines that switch in similar logic direction run adjacent to each other. This can help reduce the coupling capacitance of the adjacent lines, and results in a lower delay for a signal propagating through a wire.
Accordingly, one aspect of the present invention provides a computer implemented method of transposing a plurality of wires in a circuit design. A database is provided including a plurality of wire descriptions, each of the plurality of wire descriptions including a path traversed by the wire in the circuit design. A transposing region is defined around portions of a first and a second path corresponding to a first and a second wire description of the plurality of wire descriptions, respectively. The transposing region dividing the first path into a first leading path segment, a first transposing path segment, and a first ending path segment, and the transposing region further dividing the second path into a second leading path segment, a second transposing path segment, and a second ending path segment. The first transposing path segment is replaced with a first new transposing path segment between the first leading path segment and the second ending path segment, thereby modifying the first path for the first wire description. The second transposing path segment is replaced with a second new transposing path segment between the second leading path segment and the first ending path segment, thereby modifying the second path for the second wire description.
In another aspect of the present invention provides a computer implemented method of transposing a plurality of wires in a circuit design. A database is provided including a plurality of wire descriptions, each of the plurality of wire descriptions including a path traversed by the wire in the circuit design. A wire transposing pattern is received for application to at least a first and a second wire description of the plurality of wire descriptions. A first portion of the first wire description path is replaced with a first new portion, and replacing a second portion of the second wire description path with a second new portion such that the first wire description path and the second wire description path are transposed according to the transposing pattern.
In another aspect of the invention, an apparatus includes a processor, a memory coupled to the processor, and a circuit design program at least partially storable in the memory, and executable on the processor. The program includes a wire selection routine, a transposing region definition routine, and a replacement routine. The wire selection routine selects a plurality of wire descriptions from a database, each of the plurality of wire descriptions including a path traversed by the wire in a circuit design. The transposing region definition routine defines a transposing region around portions of a first and a second path corresponding to a first and a second wire description of the plurality of wire descriptions, respectively. The transposing region divides the first path into a first leading path segment, a first transposing path segment, and a first ending path segment, and the transposing region further divides the second path into a second leading path segment, a second transposing path segment, and a second ending path segment. The replacement routine replaces the first transposing path segment with a first new transposing path segment between the first leading path segment and the second ending path segment, thereby modifying the first path for the first wire description.